It is well known in the prior art to fabricate field effect devices such as charge coupled devices and field effect transistors incorporating the use of several levels of conductors. It has become desirable to use polycrystalline silicon (also referred to as polysilicon) instead of metal for the conductive lines. For proper operation of the resultant field effect devices, it is necessary to insulate the two levels of polysilicon from each other. Particularly, problems have been occasioned by a failure of the insulator between a sidewall of the first polysilicon layer and the second polysilicon layer. One source of failure has been caused by pin holes in the dielectric material. Another source of failure is the diffuculty in insulating the sidewall of the first polysilicon layer which is frequently under an overhanging dielectric portion. Such an overhang situation is caused by over etching of the polysilicon material when the dielectric is used as a mask. The amount of overhang is a function of polysilicon etching efficiency; but in order to assure that the polysilicon is etched completely down to the gate oxide, some overhang will always exist. This overhang inevitably produces a difficult topology for an insulating layer and a subsequent level of polysilicon to contour.
In order to avoid defects in the insulation, such as pin holes, and to avoid dielectric breakdown, it is known to increase the thickness of the insulator covering portions of the first polysilicon layer (including the critical sidewall). By conventional techniques, however, this also increases the thickness of the gate insulator (usually gate oxide). Gate oxide is usually very thin and increasing its thickness has significant adverse affects on the performance of the resultant field effect devices.